The present invention disclosed herein relates to a Phase Locked Loop (PLL) circuit, and more particularly, to a PLL circuit including automatic frequency control circuit and an operating method thereof.
When a signal is expressed as a frequency domain, it is divided into a size component representing the intensity of a signal and a phase component representing time characteristic. Since the phase component of the signal is sensitively affected by a temperature or a peripheral circuit, the phase (i.e., frequency) of the signal is easily changed. As an example, the delay of a clock signal may occur according to a signal path in transmitting of a digital signal. When signal delay occurs, since the phase of a signal is changed and thus the start and end of the clock signal is unclear, a circuit for synchronizing the start and end of the clock signal is required.
A PLL circuit is a frequency feedback circuit that stably outputs an arbitrary frequency signal synchronized with the frequency of an external input signal. The PLL circuit is widely used in an analog and digital electronic circuit system. For example, the PLL circuit is used to stably provide the oscillation frequency of a Local Oscillator (LO) for transmitting/receiving of a signal in a wireless communication system, or to generate a stable reference clock signal required for processing of a digital signal in digital circuits such as microprocessors.
Generally, a PLL circuit includes: a phase detector that compares the phase difference between an input reference signal and a feedback oscillation signal to output the compared result; a charge pump that generates a current in response to the output of the phase detector; a loop filter that generates a control voltage according to the output current of the charge pump; and a Voltage Controlled Oscillator (VCO) that generates a signal having an arbitrary frequency in response to the control voltage of the loop filter.